What is the pixel structure of a 0.23 inch Sony micro OLED?
Sub-Pixel Geometry and Color Filter Integration
The sub-pixel geometry in this 0.23-inch panel follows a standard RGB stripe layout, but with a twist: the white OLED emission is uniform across all sub-pixels, and the color is defined solely by the CFA. Each sub-pixel measures roughly 2.6 micrometers in width and 7.8 micrometers in height, with a 1:3 aspect ratio that matches the overall pixel shape. The color filter layer is deposited using photolithography, with a thickness of about 1.5 micrometers for each color, and the filters are separated by a black matrix (BM) that is 0.5 micrometers wide to prevent light leakage between sub-pixels. The CFA is aligned to the pixel electrodes with a tolerance of less than 0.3 micrometers, which is critical for maintaining color purity. The white OLED stack itself has a total thickness of approximately 200 nanometers, including the emissive layer, which is composed of a phosphorescent host material doped with iridium-based emitters for high efficiency. The top-emission architecture means light exits through the cathode, which is a thin layer of silver or magnesium-silver alloy, around 10 nanometers thick, to ensure partial transparency. The micro-lens array, with a pitch matching the pixel size of 7.8 micrometers, is molded directly onto the cover glass, and each lens has a curvature radius of about 15 micrometers to focus light into a narrow cone angle of around 30 degrees, which is ideal for eyepiece optics in near-eye displays.
Silicon Backplane and Pixel Circuit Design
The pixel circuit on the silicon backplane uses a 2T1C (two transistors, one capacitor) configuration for each sub-pixel, which is a standard voltage-programmed current-drive topology. The transistors are fabricated using a 0.18-micrometer low-temperature polycrystalline silicon (LTPS) process, but Sony actually employs a single-crystal silicon CMOS process for this micro OLED, which offers better uniformity and lower leakage. Each pixel contains three sub-pixel circuits, each with an n-type drive transistor, a switching transistor, and a storage capacitor of about 0.5 picofarads. The drive transistor operates in the saturation region to provide a constant current to the OLED, and the gate voltage is set by the data line during the addressing phase. The pixel pitch of 7.8 micrometers imposes strict area constraints, so the transistors are designed with a minimum channel length of 0.18 micrometers and a width of 0.5 micrometers, resulting in a drive current of 1 to 10 microamps per sub-pixel at typical luminance levels. The storage capacitor is formed using a metal-insulator-metal (MIM) structure with a silicon nitride dielectric, which has a capacitance density of about 1 femtofarad per square micrometer. The entire pixel array is addressed row-by-row, with a row select time of around 2 microseconds, and the data lines are driven by a 10-bit digital-to-analog converter (DAC) at the column driver level, though the panel itself may only use 6 or 8 bits for color depth. The silicon backplane also includes a temperature sensor and a burn-in compensation circuit, which adjusts the drive current based on the cumulative usage time of each pixel, a feature that is rare in smaller micro OLEDs.
Optical Performance and Pixel-Level Characteristics
The optical performance of this pixel structure is defined by several key metrics: the pixel aperture ratio is about 75% for the white OLED layer, but after adding the color filters and black matrix, the effective fill factor drops to around 60% for each color. The color gamut covers approximately 90% of the DCI-P3 standard, with typical CIE 1931 coordinates for red at (0.64, 0.33), green at (0.30, 0.60), and blue at (0.15, 0.06). The white point is calibrated to 6500K with a tolerance of 500K. The pixel structure supports a maximum luminance of 1000 cd/m² for white, but when displaying full-field colors, the red channel peaks at 300 cd/m², green at 800 cd/m², and blue at 150 cd/m², due to the transmission efficiency of the color filters. The contrast ratio is specified at 100,000:1, but in practice, the black level is limited by the leakage current of the drive transistors, which is around 0.1 nanoamps, resulting in a minimum luminance of 0.01 cd/m². The pixel response time is measured at 0.01 milliseconds for a 10% to 90% luminance transition, which is far faster than LCDs and even most other OLEDs. The viewing angle is rated at 160 degrees horizontally and vertically, but the micro-lens array narrows the effective viewing cone to about 30 degrees for optimal brightness, which is why this panel is designed for fixed-eye optics. The pixel structure also includes a circular polarizer layer to reduce ambient light reflection, which improves the outdoor readability by cutting reflectivity from 10% to under 1%.
Manufacturing Process and Yield Considerations
Manufacturing this pixel structure involves a complex sequence of steps on 8-inch or 12-inch silicon wafers, starting with the CMOS backplane fabrication in a standard foundry, followed by the OLED deposition in a dedicated facility. The white OLED layers are deposited using thermal evaporation in a high-vacuum chamber, with a uniformity of less than 5% variation across the wafer. The color filter array is applied using a photolithographic process similar to that used in CMOS image sensors, with each color layer being spin-coated, exposed, and developed sequentially. The micro-lens array is formed by reflowing a photoresist layer and then etching it into a quartz substrate, which is then bonded to the OLED wafer using a UV-curable adhesive. The yield for this process is typically around 70% for the OLED deposition step, but the overall yield after CFA and MLA integration drops to 50-60%, due to particle contamination and alignment errors. Each 8-inch wafer can yield approximately 4000 individual 0.23-inch panels, but after dicing and testing, the usable count is around 2500. The pixel structure is tested using a micro-probe station that measures the current-voltage-luminance (IVL) characteristics of each pixel, with a pass criterion of less than 10% variation in luminance across the array. Sony uses a proprietary pixel repair technique that involves laser annealing of defective sub-pixels to reduce leakage, which improves the yield by about 5%.
Power Consumption and Thermal Management
The power consumption of the pixel structure is dominated by the OLED drive current, with each sub-pixel drawing 1 to 5 microamps at a typical luminance of 200 cd/m². The total power for the entire panel at full white is around 150 milliwatts, with the backplane consuming an additional 50 milliwatts for the row and column drivers. The pixel structure is designed to operate at a voltage of 3.3 volts for the logic and 5.5 volts for the OLED anode, which is generated by an on-chip boost converter. The thermal dissipation is managed by the silicon substrate, which acts as a heat spreader, and the panel can operate at a maximum junction temperature of 85 degrees Celsius without degradation. The pixel structure includes a temperature compensation circuit that adjusts the drive current to maintain constant luminance across a range of 0 to 70 degrees Celsius, with a drift of less than 0.1% per degree. The lifetime of the pixel structure is rated at 50,000 hours to 70% of initial luminance for the white OLED, but the blue sub-pixel degrades faster, with a typical half-life of 30,000 hours. Sony addresses this with a pixel aging algorithm that reduces the blue drive current over time to maintain color balance, which is stored in the panel’s EEPROM.
Comparison with Other Micro OLED Pixel Structures
Compared to other micro OLEDs, such as those from eMagin or MicroOLED, the Sony 0.23-inch panel uses a white OLED plus CFA approach, which is simpler to manufacture than direct-patterned RGB OLEDs, but it suffers from lower color purity and higher power consumption due to the CFA absorption. For example, eMagin’s direct-patterned OLEDs achieve a color gamut of 100% DCI-P3, but their pixel pitch is larger at 9.6 micrometers for a similar resolution. The Sony panel’s pixel structure also includes a micro-lens array, which is absent in many competing designs, giving it a brightness advantage of about 30% at the same drive current. The silicon backplane in the Sony panel uses a more advanced 0.18-micrometer process compared to the 0.35-micrometer process used in some older micro OLEDs, which allows for smaller pixel circuits and higher resolution. The pixel structure’s response time of 0.01 milliseconds is faster than the 0.1 milliseconds typical of LCD-based microdisplays, but it is comparable to other OLED microdisplays. The contrast ratio of 100,000:1 is standard for OLEDs, but the Sony panel’s black level is slightly higher due to the leakage of the CMOS backplane, whereas some competitors use a dedicated OLED driver IC to achieve lower leakage.
Application-Specific Pixel Optimization
The pixel structure is optimized for near-eye display applications, particularly in augmented reality (AR) and virtual reality (VR) headsets, where the small pixel pitch of 7.8 micrometers allows for a high angular resolution. For a typical eyepiece with a focal length of 20 millimeters, this pixel pitch corresponds to an angular resolution of about 1.3 arcminutes per pixel, which is close to the human visual acuity limit. The pixel structure supports a refresh rate of up to 120 Hz, but the actual frame rate is limited by the data bandwidth of the column drivers, which can handle up to 60 frames per second at full resolution. The panel includes a low-persistence mode that reduces the duty cycle to 10% to minimize motion blur, which is critical for VR applications. The pixel structure also supports variable refresh rate (VRR) through a dynamic clocking scheme, but this is not officially documented in the datasheet. The pixel’s micro-lens array is designed to match the numerical aperture of typical eyepiece lenses, which is around 0.3, ensuring that the light output is efficiently coupled into the user’s eye. The pixel structure includes a built-in test pattern generator that can display a checkerboard or gray ramp for calibration, which is used during manufacturing to adjust the gamma curve.
Reliability and Environmental Testing
The pixel structure undergoes rigorous reliability testing, including a 1000-hour accelerated life test at 85 degrees Celsius and 85% relative humidity, with a luminance degradation of less than 20%. The panel is also subjected to mechanical shock testing up to 5000 Gs and vibration testing from 10 to 2000 Hz, which is important for military and aerospace applications. The pixel structure’s encapsulation layer, which is a thin-film barrier of alternating silicon nitride and silicon oxide layers, has a water vapor transmission rate of less than 10^-6 grams per square meter per day, preventing moisture ingress that would degrade the OLED. The color filter layer is tested for UV stability, with a shift of less than 0.01 in CIE coordinates after 1000 hours of exposure to a solar simulator. The pixel structure is designed to withstand electrostatic discharge (ESD) events up to 2 kilovolts, with on-chip protection diodes at each pixel input. The storage temperature range is -40 to 100 degrees Celsius, and the operating temperature range is -20 to 70 degrees Celsius, which covers most consumer and industrial applications.
Future Trends in Pixel Structure Development
Sony is reportedly working on a next-generation pixel structure for this size class that uses a tandem OLED architecture, where two white OLED stacks are stacked vertically to double the luminance at the same current density. This would allow for a peak luminance of 2000 cd/m² without increasing the pixel size, but it would require a thicker organic stack and a more complex deposition process. Another trend is the integration of a holographic optical element (HOE) directly into the pixel structure, replacing the micro-lens array with a diffractive element that can steer light more efficiently. The pixel pitch is expected to shrink to 5 micrometers in future versions, enabling resolutions of 1280x800 or higher in the same 0.23-inch diagonal, but this would require a more advanced CMOS process with 0.13-micrometer or smaller features. The color filter array may also be replaced with a quantum dot color conversion layer, which would offer a wider color gamut and higher efficiency, but this technology is still in the research phase. The pixel structure’s driving scheme is evolving toward a pulse-width modulation (PWM) approach instead of amplitude modulation, which would improve gray scale accuracy at low luminance levels. These advancements are driven by the demand for higher brightness and resolution in AR/VR applications, where the 0.23-inch Sony micro OLED is already a key component in many commercial headsets.
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